Senior Digital Design Engineer

Cambridge, UK | Full-time | Permanent | Hybrid 

Salary: £70,000 to £90,000 DOE + Bonus + Benefits

 The salary range for this role is broad, as we are able to consider varying levels of experience.  Any offer made will carefully take into account level of experience (including relevant industry experience), transferable relevant skills and previous relevant achievements.

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.  

About us 

Riverlane’s mission is to master quantum error correction (QEC) and unlock a new age of human progress. From advances in material and climate science, to complex chemistry simulation for new drug design, quantum computers will help humanity solve some of its most important challenges. But without QEC, the industry’s defining technical challenge, such breakthroughs can never be achieved.  Riverlane is the world leader in QEC technology. QEC is a complex problem that requires a range of skills, talent and passion.  

Having raised more than $125M in funding to date to accelerate our cutting-edge R&D in quantum error correction (QEC), Riverlane partners with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.  

About the role 

We have a fantastic opportunity for an experienced Digital Design Engineer to join us as we build the world’s first quantum error correction (QEC) stack. Don’t have a background in quantum computing? Not a problem!  This cutting-edge technology requires a wide range of skills and disciplines, including classical computing skills. You will learn quantum computing along the way.   

As a senior-level Digital Design Engineer at Riverlane, you will help develop a multi-FPGA, low-latency, high throughput system that needs to perform complex operations, in a predictable and guaranteed way. You will use your knowledge and expertise to support more junior engineers, interact with software and identify novel solutions to our challenging problems.

This is an exceptional opportunity to join Riverlane's Hardware team, where you will develop cutting-edge decoding algorithms and tackle complex data routing and processing challenges while maximizing system throughput and minimizing latency.

Our mission is exciting, but complex. It requires teams with a wide range of skills and perspectives, that communicate well and collaborate effectively to achieve truly innovative solutions.    

You will thrive in an environment where knowledge sharing and continuous learning are the norm. We are moving fast in a brand new market, where requirements can change quickly as the technology evolves, so the ability to adapt is critical.  

What you will do 

• Performance and area optimisation of our RTL
• Designing deeply pipelined modules capable of operating reliably at very high clock speeds
• Reviewing specifications and RTL produced by junior engineers

What we need 

• Experience with state-of-the-art FPGA platforms (e.g. AMD/Xilinx MPSoCs/RFSoCs, Altera Stratix 7 or Stratix 10)  
• Proven professional experience in at least one of the following areas: 
• Implementation of modern classical decoders on FPGA/ASIC e.g. LDPC, turbo-codes; 

• Architecture of System on Chip solutions, with at least one CPU and custom accelerators; 
• Large-scale, complex systems on FPGA/ASIC

• Proven capability to test, debug and improve complex systems  

• Ability to convert product requirements into technical specifications to document and share your work  

• A curious nature and a passion for learning and continuous improvement  

• Excellent communication skills, with the ability to work both independently and collaboratively as part of a team  

Even better if you have...

• Experience with ASIC environments (<48nm)

What can you expect from us 

• A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme  

• Equity, so that our team can share in the long-term success of Riverlane  

• 28 days annual leave, plus bank holidays and enhanced family leave  

• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities  

• A learning environment that encourages individual, team and company growth and development, including a regular programme of learning events and training and conference budgets 

How to apply 

Please upload a CV and covering letter by clicking 'Apply'. Your covering letter should explain why you are applying for the job and what skills and experience you can bring to the role. 

We review CVs as we receive them and interview as soon as we have applications that look like a good match. We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. 

If you have any queries, please contact jobs@riverlane.com. 

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. 

Women and other underrepresented groups may be less likely to apply for a role unless they meet all or nearly all of the requirements.  If this applies to you, we still encourage you to apply - you may be a great fit, even if you don’t meet every single qualification. We’d love to hear from you. 

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help. 

GDPR notice: Riverlane collects and processes personal data in accordance with applicable data protection laws. If you are a European Job Applicant see the privacy notice for further details.