Job Application for Lead Physical Design Engineer at Fractile

Lead Physical Design Engineer

Fractile is building the silicon, systems and software to break through the memory wall, the fundamental hardware constraint standing between today's AI and what comes next.

The frontier of AI is no longer a research problem. The tasks AI can complete are doubling in complexity every six to seven months and the tokens required to complete them are scaling with it. Sequential reasoning, the kind that can't be parallelised away, means the internal clock speed of inference systems is the critical constraint. What stands between where we are today and the future potential of AI isn't smarter algorithms; it's the hardware to run them fast enough to matter.

Today's chips are hitting their wall. We're building the ones that don't.

Fractile is seeking to increase the clock speed of global progress, one chip at a time.

We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:

Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
Own power planning and analysis, addressing IR drop, electromigration, and related effects.
Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
Mentor junior engineers and contribute to building strong physical design practices across the team.
Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Preferred Qualifications:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign-off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Proven ability to take ownership of complex designs and drive them to completion.
• Experience mentoring engineers and leading physical design efforts.
• Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high-performance computing (HPC), AI accelerators, or networking chips.
• Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

How we work:

Ownership and execution: you will have full agency to drive your work forward
Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped
About us:

• Founded 2022, we're 100+ people across London and Bristol, in the heart of the UK's frontier AI ecosystem, and growing fast.

• We offer competitive salaries, meaningful equity, and standard company benefits.

• We believe the hardest problems get solved by the broadest range of minds. We actively encourage applications from underrepresented groups in hardware and software engineering.

• Hybrid working; 2-3 days in our London and Bristol offices.

Export controls:

Our work involves technologies subject to UK and international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We'll be transparent about this throughout the hiring process.

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Lead Physical Design Engineer

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